This invention relates generally to a process for fabricating CMOS devices, and more specifically to a process for forming LDD CMOS devices with a reduced mask count and an improved manufacturability.
A problem called "hot carrier instability" has been well documented for MOS devices, and especially those MOS devices which have a narrow spacing between source and drain. The problem occurs as a result of high electrical fields, particularly near the drain, that cause energetic carriers ("hot carriers") to be injected into the gate or the substrate. The injection of hot carriers into the gate can cause oxide charging which manifests itself, over time, as a threshold voltage instability and a degraded device performance.
A number of solutions have been proposed for mitigating the problems of hot carrier injection. The most promising of these solutions is the use of a lightly doped drain (LDD) structure. This solution is discussed, for example, by Takeda, et al., "Submicrometer MOSFET Structure for Minimizing Hot-Carrier Generation", IEEE Transactions on Electron Devices, Vol. ED-29, No. 4, April 1982, pp. 611-618. The LDD structure consists of lightly doped source/drain regions adjacent the gate electrode with heavily doped source/drain regions laterally displaced from the gate electrode. The lightly doped region, which is driven just under the gate electrode, minimizes the injection of hot carriers and the heavily doped region provides a low resistance region which is easily contacted.
To be useful, the LDD structure used in a practical device must be fabricated by a process which is self-aligning. This requirement has led to the use of sidewall spacers which space the heavily doped source/drain regions a prescribed distance away from the gate electrode without relying on a critical photolithographic alignment step. The lightly doped regions are implanted using the gate electrode as an implantation mask. The sidewall spacer is formed by depositing a conformal layer of a spacer forming material overlying the gate electrodes. The spacer forming material is anisotropically etched to leave the material on all vertical surfaces including the edges of the gate electrodes. Spacers formed in this manner are then used as an ion implantation mask to space the heavy source/drain implant a lateral distance from the edge of the gate electrode with the lateral displacement determined by the thickness of the sidewall spacer material.
The use of the above described technology to form LDD CMOS circuit structures has generally led to the necessity for a large number of process steps. Additional process steps ultimately increase the cost of a device and should, if possible, be avoided. The above referenced application serial number 47,589 provides one process for making LDD CMOS devices with a reduced number of process steps. The process therein disclosed, however, relies on a differential oxidation of heavily doped regions versus lightly doped regions. The process is also inflexible in requiring certain annealing steps to be combined. Still further, the process requires additional deposition and sidewall formation steps.
Accordingly, a need existed for a improved process for forming LDD CMOS structures which would overcome the disadvantages of the prior art processes.
It is therefore an object of this invention to provide an improved process for forming LDD CMOS structures using a single LDD lithography mask.
It is another object of this invention to provide an improved LDD CMOS process to provide either single or double LDD structures.
It is yet another object of this invention to provide an improved process for forming LDD CMOS structures which allows flexibility in N-type and P-type thermal cycles.
It is a further object of this invention to provide an improved process for forming LDD CMOS structures in which differential oxidation of differently doped material is not critical to the process.
It is a still further object of the invention to provide an improved process for forming CMOS structures which reduces the number of processing steps.